1. Field of the Invention
This invention relates generally to metal-oxide-silicon (MOS) semiconductor structures and devices and methods for fabricating such devices, and more specifically to semiconductor structures and devices having a complementary metal-oxide-silicon (CMOS) construction wherein the n-channel metal-oxide-silicon (NMOS) and p-channel metal-oxide-silicon (PMOS) devices are provided with channel regions having different crystal plane orientations for enhancing the relative performance of the NMOS and/or the PMOS devices and methods for fabricating such channel regions on a single semiconductor substrate.
2. Background Art
Semiconductor devices are fabricated from multiple layers of conducting, insulating, and semiconducting material layers and patterns. With respect to single crystal semiconductor materials in particular, the properties of such layers depend in part on the crystal orientation of the exposed surfaces into which dopants are implanted and/or additional patterns are formed.
In general, the most commonly utilized crystal orientation for silicon wafers used in VLSI (Very Large Scale Integration) device fabrication processes is the (100) crystal orientation. The semiconductor manufacturing industry has tended to adopt the (100) surface orientation over the (111) crystal orientation in part to take advantage of the lower surface state density on thermally oxidized surfaces associated with the (100) surface. For example, a surface having a (111) crystal orientation may exhibit a surface state charge density of approximately 5×1011 e/cm2, while a corresponding surface having a (100) crystal orientation may exhibit a surface state charge density of approximately 9×1010 e/cm2, a reduction of about 80%. Similarly, surfaces having a (110) crystal orientation can exhibit a surface state charge density of approximately 2×1011 e/cm2, still approximately twice the surface charge density of corresponding (100) surfaces.
As will be appreciated by those skilled in the art, the lattice planes and directions relation to a particular crystalline structure are commonly expressed using Miller indices, i.e., a grouping of three numbers h, k and l that are set off by additional surrounding characters for indicating a specific direction, i.e., [1,−1,0], a family of equivalent directions, i.e., <110>, a specific plane, i.e., (110), or a family of equivalent planes, i.e., {110}. This notation may be utilized with various crystal unit cells including simple cubic (SC), body-centered cubic (BCC), face-centered cubic (FCC) and diamond (DIA or C) which may be considered a modified FCC. Silicon and germanium, for example, are typically considered to have a diamond crystalline structure.
Surface state density can be a particularly important consideration for NMOS technologies as a result of the difficulties associated with higher surface state density levels for accurately controlling the active and parasitic device threshold voltages for devices fabricated on such surfaces. As semiconductor device fabrication methods and device design have improved, the differences in surface state densities have become somewhat less problematic. For example, the difference in surface state density levels between surfaces having (100) and (110) crystal orientations may translate a voltage offset of about 0.1 volts in the active device threshold voltage. Offsets of this magnitude may be and are routinely compensated through the use of a surface threshold voltage ion implant. Another benefit for NMOS devices formed on surfaces having lower surface state charge densities flows from improved electron mobility in inversion layers formed on surfaces having a (100) crystal orientation when compared with surfaces.
As illustrated in FIGS. 1A and 1B, electron and hole mobility can vary widely with the orientation of the channel region surface and the direction of the carrier flow within that channel region. As reflected in the relative mobility values illustrated in FIGS. 1A and 1B, a particular combination of crystal orientation and carrier direction that improves hole mobility tends to suppress electron mobility simultaneously. As a result, while electron mobility is higher on (100) substrates, particularly with current flow in the <110> direction, hole mobility is highest on (110) substrates with current flow in the <110> direction. The relative mobility of the corresponding carriers, in turn, affects the sizing and/or performance of the resulting semiconductor devices and tends compromise the performance of either the NMOS or the PMOS devices when the devices are formed in semiconductor regions having the same crystal orientation.
Semiconductor surfaces having a (110) crystal plane orientation have been investigated, particularly in the context of Silicon On Insulator (SOI) technologies, by using (110) substrate wafers and/or by inducing recrystallization of the surface of a substrate wafer to produce regions having a (110) crystal orientation. These efforts, however, have required adaptation of the structures and processes that have been developed for the more standard (100) crystalline plane orientation and/or require difficult and/or costly additional processing steps and procedures.
Accordingly, there remains a need for substrate structures and fabrication methods that can improve carrier mobility in one or both of the NMOS and PMOS semiconductor devices and that achieve these improvements using processes that are generally compatible with conventional processing materials, techniques and methods and without necessitating unduly complex or costly additional processing steps.